Chip Design

Responsible: Prof.-Dr. Thilo Pionteck

The lecture provides an introduction to the design of application-specific chips (ASICs). Starting from a register transfer description of a digital circuit, all essential design steps necessary for creating a chip layout are covered. In addition to clarifying the individual design steps through the use of CAD tools, the physical background and underlying algorithms are also covered.

Theoretical and practical exercises are offered for the lecture. The theoretical exercises deepen the understanding of the underlying algorithms of the design steps. In the practical exercises, the design steps can be carried out independently using small sample designs. For this purpose, we use the 45 nm Generic Process Design Kit and CAD tools from Cadence.

The topics in detail:

• CMOS manufacturing
• Standard cell design
• Synthesis
• Partitioning
• Floorplanning
• Placement
• Routing
• Power planning
• Design for testability
• Automatic test pattern generation

Lecture language: German

As of July 31, 2025