News
HTI in Tampere: Three Papers at NorCAS 2026
From October 20 to 21, 2026, the “IEEE Nordic Circuits and Systems Conference” (NorCAS) took place in Tampere, Finland. Our chair was represented with three presentations:
- Vincent Sprave presented his work “Enabling Mixed-Criticality Applications for the Versal AI-Engines” in a talk.
- Max Tzschoppe presented the poster “Fair Evaluation of 3D NoCs Using Long-Range Links in Heterogeneous M3D SoCs: Why Uniform Random Traffic Misleads.”
- Vitalii Burtsev presented the poster “On the Design of a Slow Control Interlock System for the European GateMate FPGA.”
Congratulations to Vincent, Max, and Vitalii on this wonderful publication success! We are proud that our research on mixed-criticality systems, 3D NoCs, and FPGA-based control systems was showcased at an international conference. We wish you a wonderful time in Finland, stimulating discussions with the community, and a safe trip home!
HTI goes to Finland!
We're proud to announce that three papers from our Chair have been accepted for the IEEE Nordic Circuits and Systems Conference (NorCAS), taking place 20–21 October 2026 in Tampere, Finland.
Congratulations to our authors:
- „Enabling Mixed-Criticality Applications for the Versal AI-Engines“ – Vincent Sprave
- „Fair Evaluation of 3D NoCs Using Long-Range Links in Heterogeneous M3D SoCs: Why Uniform Random Traffic Misleads“ – Max Tzschoppe
- „On the Design of a Slow Control Interlock System for the European GateMate FPGA“ – Vitalii Burtsev
A great result for our team and a valuable opportunity to present our latest work to the Nordic and international circuits-and-systems community. We're looking forward to the discussions in Tampere!
First conference, no paper — and that’s exactly how it’s supposed to be.
This week, our Ph.D. student Carlo Schafflik is attending FPL 2026 in Ghent, the 36th “International Conference on Field-Programmable Logic and Applications,” hosted by Ghent University from September 7 to 11.
He’s there without presenting his own work—and that’s our approach: Every doctoral student in our department attends FPL during their first year, one of the leading international conferences in the fields of FPGAs and reconfigurable hardware. Not as a reward for a finished result, but as a starting point.
After all, nothing conveys the current state of research as well as a few days spent among the people who are driving it forward: listening, asking questions, making connections, and developing a sense of one’s own standing.
Carlo’s plan is simple: soak it all in this year—and be on the program himself next year.
Have fun and enjoy great conversations in Ghent, Carlo!
RAW Workshop 2026 Paper published
We are happy to announce that our paper, "A Lightweight Slow Control Interlock System Targeting the European GateMate™ FPGA," has been published in the IEEE IPDPSW 2026 proceedings!
This work focuses on two key aspects: our preliminary results on an FPGA-centric lightweight slow control interlock system, and our hands-on experience porting the design to the GateMate™ FPGA by Cologne Chip AG. We also used an open-source FPGA design flow based on Yosys, nextpnr-himbaechel, GHDL, and openFPGAloader.
This was a great opportunity to explore the maturity and potential of an open-source toolchain for a European FPGA platform.
Many thanks to my co-authors, Daniel Anders, Vitalii Burtsev, Daniele Passaretti, Christof Pfannenmüller, and Fabian Lurz.