News

This week, our Ph.D. student Carlo Schafflik is attending FPL 2026 in Ghent, the 36th “International Conference on Field-Programmable Logic and Applications,” hosted by Ghent University from September 7 to 11.

He’s there without presenting his own work—and that’s our approach: Every doctoral student in our department attends FPL during their first year, one of the leading international conferences in the fields of FPGAs and reconfigurable hardware. Not as a reward for a finished result, but as a starting point.

After all, nothing conveys the current state of research as well as a few days spent among the people who are driving it forward: listening, asking questions, making connections, and developing a sense of one’s own standing.

Carlo’s plan is simple: soak it all in this year—and be on the program himself next year.

Have fun and enjoy great conversations in Ghent, Carlo!

We are happy to announce that our paper, "A Lightweight Slow Control Interlock System Targeting the European GateMate™ FPGA," has been published in the IEEE IPDPSW 2026 proceedings!

This work focuses on two key aspects: our preliminary results on an FPGA-centric lightweight slow control interlock system, and our hands-on experience porting the design to the GateMate™ FPGA by Cologne Chip AG. We also used an open-source FPGA design flow based on Yosys, nextpnr-himbaechel, GHDL, and openFPGAloader.

This was a great opportunity to explore the maturity and potential of an open-source toolchain for a European FPGA platform.

Many thanks to my co-authors, Daniel Anders, Vitalii Burtsev, Daniele Passaretti, Christof Pfannenmüller, and Fabian Lurz.

The “Heterogeneous Computing” student lab at the Chair of Hardware-Oriented Computer Engineering has been completely redesigned. At 15 modern workstations, students can independently explore and practically test the various processing principles of hardware accelerators. The lab serves as the foundation for the master’s course of the same name.
Each workstation is equipped with a mini-PC based on the AMD Ryzen AI 9 HX 370, which combines CPU, GPU, and AI units (AI engines) on a single chip. The setup is complemented by the AUP-ZU3 FPGA development board, which was co-funded with the kind support of the  AMD/Xilinx University Program and provides an introduction to the world of reconfigurable hardware.
Using an end-to-end image processing application, students explore the core concepts of heterogeneous computing systems throughout the course: parallelization across the processor’s CPU cores, acceleration on the integrated GPU, the design of dedicated hardware accelerators using high-level synthesis (HLS) on the FPGA, and the programming of the Ryzen processor’s AI engines. This allows students to directly compare the various acceleration concepts and learn about them in the context of the current state of the art.