EmuNoC - hybrid emulation for fast and flexible network-on-chip prototyping on FPGAs

Tan, Yee Yang; Staudigl, Felix; Jünger, Lukas; Drewes, Anna; Leupers, Rainer; Joseph, Jan Moritz

In: Konferenz: 32nd International Conference on Field-Programmable Logic and Applications, FPL, Belfast, United Kingdom, 29 August 2022 - 02 September 2022, 2022 32st International Conference on Field-Programmable Logic and Applications (FPL 2022) - Piscataway, NJ: IEEE; Göhringer, Diana *1980-* . - 2023, S. 334-341

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3D Interconnect Architectures for Heterogeneous Technologies - Modeling and Optimization

Bamberg, Lennart; Joseph, Jan Moritz; García-Ortiz, Alberto; Pionteck, Thilo

In: Cham: Imprint: Springer, 2022., 1st ed. 2022., 1 Online-Ressource(XXV, 395 p. 102 illus., 100 illus. in color.) - (Springer eBook Collection)

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Architecture, dataflow and physical design implications of 3D-ICs for DNN-accelerators

Joseph, Jan Moritz; Samajdar, Ananda; Zhu, Lingjun; Leupers, Rainer; Lim, Sung Kyu; Pionteck, Thilo; Krishna, Tushar

In: Proceedings of the Twenty Second International Symposium on Quality Electronic Design/ ISQED - [Piscataway, NJ]: IEEE; Ghosh, Swaroop . - 2021, S. 60-66

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Ratatoskr - an open-source framework for in-depth power, performance, and area analysis and optimization in 3D NoCs

Joseph, Jan Moritz; Bamberg, Lennart; Hajjar, Imad; Perjikolaei, Behnam Razi; García-Ortiz, Alberto; Pionteck, Thilo

In: ACM transactions on modeling and computer simulation/ Association for Computing Machinery - New York, NY: ACM Press, Bd. 32 (2021), 1, insges. 21 S.

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Optimising operator sets for analytical database processing on FPGAs

Drewes, Anna; Joseph, Jan Moritz; Gurumurthy, Balasubramanian; Broneske, David; Saake, Gunter; Pionteck, Thilo

In: Applied Reconfigurable Computing. Architectures, Tools, and Applications: 16th International Symposium, ARC 2020, Toledo, Spain, April 13, 2020, Proceedings - Cham: Springer International Publishing . - 2020, S. 30-44 - (Lecture Notes in Computer Science; volume 12083)

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Application-specific SoC design using core mapping to 3D mesh NoCs with nonlinear area optimization and simulated annealing

Joseph, Jan Moritz; Ermel, Dominik; Bamberg, Lennart; García-Oritz, Alberto; Pionteck, Thilo

In: Technologies: open access journal - Basel: MDPI, Bd. 8 (2020), 1, insges. 10 S.

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Area optimization with non-linear models in core mapping for system-on-chips

Joseph, Jan Moritz; Ermel, Dominik; Drewes, Anna; Bamberg, Lennart; Garcia-Oritz, Alberto; Pionteck, Thilo

In: 2019 8th International Conference on Modern Circuits and Systems Technologies (MOCAST): May 13-15, 2019, Aristotle University Research Dissemination Center (KEDEA), Thessaloniki, Greece/ International Conference on Modern Circuits and Systems Technologies - [Piscataway, NJ]: IEEE . - 2019

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Survey on FPGAs in medical radiology applications - challenges, architectures and programming models

Passaretti, Daniele; Joseph, Jan Moritz; Pionteck, Thilo

In: Konferenz: International Conference on Field-Programmable Technology, ICFPT, Tianjin, China, 09-13 December 2019, 2019 International Conference on Field-Programmable Technology/ ICFPT - Piscataway, NJ: IEEE . - 2019, S. 279-282

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System-level optimization of network-on-chips for heterogeneous 3D system-on-chips

Joseph, Jan Moritz; Ermel, Dominik; Bamberg, Lennart; García Oritz, Alberto; Pionteck, Thilo

In: Konferenz: IEEE 37th International Conference on Computer Design, ICCD, Abu Dhabi, United Arab Emirates, 17-20 November 2019, 2019 IEEE International Conference on Computer Design/ IEEE International Conference on Computer Design - Piscataway, NJ: IEEE . - 2019, S. 409-412

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Hardware-accelerated index construction for semantic web

Blochwitz, Christopher; Wolff, Julian; Bereković, Mladen; Heinrich, Dennis; Groppe, Sven; Joseph, Jan Moritz; Pionteck, Thilo

In: Konferenz: 2018 International Conference on Field-Programmable Technology, FPT, Naha, Okinawa, Japan, 10-14 December 2018, 2018 International Conference on Field-Programmable Technology/ International Conference on Field-Programmable Technology - Piscataway, NJ: IEEE . - 2019

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Efficient inter-kernel communication for OpenCL database operators on FPGAs

Drewes, Anna; Joseph, Jan Moritz; Gurumurthy, Bala; Broneske, David; Saake, Gunter; Pionteck, Thilo

In: 2018 International Conference on Field-Programmable Technology (FPT) - [Piscataway, NJ]: IEEE, 2019[Konferenz: 2018 International Conference on Field-Programmable Technology, FPT, Naha, Okinawa, Japan, 10-14 December 2018]

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Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment

Bamberg, Lennart; Joseph, Jan Moritz; Pionteck, Thilo; García Ortiz, Alberto

In: Integration, the VLSI journal - Amsterdam [u.a.]: Elsevier Science, 1983, Bd. 67.2019, S. 60-72

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Simulation environment for link energy estimation in networks-on-chip with virtual channels

Joseph, Jan Moritz; Bamberg, Lennart; Hajjar, Imad; Schmidt, Robert; Pionteck, Thilo; García Ortiz, Alberto

In: Integration, the VLSI journal - Amsterdam [u.a.]: Elsevier Science, 1983 . - 2019[Online first]

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NoCs in heterogeneous 3D SoCs - co-design of routing strategies and microarchitectures

Joseph, Jan Moritz; Bamberg, Lennart; Ermel, Dominik; Perjikolaei, Behnam Razi; Drewes, Anna; García Ortiz, Alberto; Pionteck, Thilo

In: IEEE access/ Institute of Electrical and Electronics Engineers - New York, NY: IEEE, Bd. 7 (2019), S. 135145-135163

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Networks-on-Chip for heterogeneous 3D Systems-on-Chip

Joseph, Jan Moritz; Pionteck, Thilo

In: Magdeburg, 2019, xiv, 248 Seiten, Illustrationen, Diagramme, 30 cm[Literaturverzeichnis: Seite 235-246]

Coding-aware link energy estimation for 2D and 3D networks-on-chip with virtual channels

Bamberg, Lennart; Joseph, Jan Moritz; Schmidt, Robert; Pionteck, Thilo; García Ortiz, Alberto

In: 2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018): 2-4 July 2018, Spain/ IEEE International Symposium on Power and Timing Modeling, Optimization and Simulation - Piscataway, NJ: IEEE, 2018; IEEE International Symposium on Power and Timing Modeling, Optimization and Simulation (28.:2018) . - 2018, S. 222-228[Symposium: IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2018, Platja d'Aro, Spain, 2-4 July 2018]

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Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS

Joseph, Jan Moritz; Mey, Morten; Ehlers, Kristian; Blochwitz, Christopher; Winker, Tobias; Pionteck, Thilo

In: 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig17): Cancun, Mexico, December 4-6, 2017 - Piscataway, NJ: IEEE, insges. 8 S., 2018[Kongress: International Conference on Reconfigurable Computing and FPGAs, ReConFig17, Cancun, Mexico, December 4-6, 2017]

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Continuous live-tracing as debugging approach on FPGAs

Blochwitz, Christopher; Klink, Raphael; Joseph, Jan Moritz; Pionteck, Thilo

In: 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig17): Cancun, Mexico, December 4-6, 2017 - Piscataway, NJ: IEEE, insges. 8 S., 2018[Kongress: International Conference on Reconfigurable Computing and FPGAs, ReConFig17, Cancun, Mexico, December 4-6, 2017]

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An FPGA-based prototyping framework for Networks-on-Chip

Drewes, Tobias; Joseph, Jan Moritz; Pionteck, Thilo

In: 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig17): Cancun, Mexico, December 4-6, 2017 - Piscataway, NJ: IEEE, insges. 7 S., 2018[Kongress: International Conference on Reconfigurable Computing and FPGAs, ReConFig17, Cancun, Mexico, December 4-6, 2017]

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Specification of simulation models for NoCs in heterogeneous 3D SoCs

Joseph, Jan Moritz; Bamberg, Lennart; Krell, Gerald; Hajjar, Imad; Garcia-Oritz, Alberto; Pionteck, Thilo

In: Proceedings of the 13th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC): July 9th-11th, 2018, Lille, France - Piscataway, NJ: IEEE, insges. 8 S.[Symposium: 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Lille, France, July 9th-11th, 2018]

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Contentious live-tracing as debugging approach on FPGAS

Blochwitz, Christopher; Klink, Raphael; Joseph, Jan Moritz; Pionteck, Thilo

In: ReConFig'17 : 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ : IEEE [General session; Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig'17, Cancun, Mexico, December 4-6, 2017]

Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS

Joseph, Jan Moritz; Mey, Morten; Ehlers, Kristian; Blochwitz, Christopher; Winker, Tobias; Pionteck, Thilo

In: ReConFig'17 : 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ : IEEE [Poster session B; Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig'17, Cancun, Mexico, December 4-6, 2017]

Design method for asymmetric 3D interconnect architectures with high level models

Joseph, Jan Moritz; Bamberg, Lennart; Wrieden, Sven; Ermel, Dominik; García-Oritz, Alberto; Pionteck, Thilo

In: 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017) : July 12-14, 2017, Madrid, Spain : proceedings - [Piscataway, NJ] : IEEE, insges. 8 S. [Symposium: 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2017, Madrid, Spain, July 12-14 2017]

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Hardware-accelerated radix-tree based string sorting for big data applications

Blochwitz, Christopher; Wolff, Julian; Joseph, Jan Moritz; Werner, Stefan; Heinrich, Dennis; Groppe, Sven; Pionteck, Thilo

In: Architecture of Computing Systems - ARCS 2017 - 30th International Conference, Vienna, Austria, April 36, 2017, Proceedings - Cham: Springer, 2017 . - 2017, S. 47-58 - (Lecture Notes in Computer Science; 10172)[Konferenz: 30th International Conference on Architecture of Computing Systems, ARCS 2017, Vienna, Austria, April 3-6, 2017]

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An FPGA-based prototyping framework for networks-on-Chip

Drewes, Tobias; Joseph, Jan Moritz; Pionteck, Thilo

In: ReConFig'17 : 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ : IEEE [poster session A; Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig'17, Cancun, Mexico, December 4-6, 2017]

Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs$Jan Moritz Joseph, ChristopherBlochwitz, Alberto García-Ortiz, Thilo Piontecka

Joseph, Jan Moritz; Blochwitz, Christopher; García Ortiz, Alberto; Pionteck, Thilo

In: Microprocessors and microsystems - Amsterdam [u.a.]: Elsevier, 1979, Bd. 48.2017, S. 36-47

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Hardware-accelerated pose estimation for embedded systems using vivado HLS

Joseph, Jan Moritz; Winker, Tobias; Ehlers, Christian; Blochwitz, Christopher; Pionteck, Thilo

In: ReConFig: 2016 International Conference on Reconfigurable Computing and FPGAs : November 30 - December 2, Cancun, Mexico - Piscataway, NJ: IEEE[Kongress: 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig, Cancun, Mexico, November 30 - December 2, 2016]

Adaptive allocation of default router paths in Network-on-Chips for latency reduction

Joseph, Jan Moritz; Blochwitz, Christioher; Pionteck, Thilo

In: Proceedings of the 2016 International Conference on High Performance Computing & Simulation (HPCS 2016): July 18-22, 2016, Innsbruck, Austria - Piscataway, NJ: IEEE[Kongress: 2016 International Conference on High Performance Computing & Simulation (HPCS), Innsbruck, Austria, 18-22 July, 2016]

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A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip

Joseph, Jan Moritz; Wrieden, Sven; Blochwitz, Christopher; García Ortiz, Alberto; Pionteck, Thilo

In: 2016 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoc): June 27-29, 2016, Tallinn, Estonia - [Piscataway, NJ]: IEEE[Kongress: 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoc), 27. - 29.June 2016, Tallinn, Estonia]

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Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs

Joseph, Jan Moritz; Blochwitz, Christopher; Pionteck, Thilo; Garcia-Ortiz, Alberto

In: 2015, S. 1-4, 10.1109/NORCHIP.2015.7364370

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A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling

Joseph, Jan Moritz; Pionteck, Thilo

In: 2014, S. 1-6, 10.1109/ISSOC.2014.6972440

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