Exploring hardware accelerators capabilities in UHF-MRI data processing
This thesis explores existing accelerator architectures, such as GPUs, TPUs, FPGAs, and adaptive SoCs, for real-time UHF-MRI applications. The student will identify bottlenecks using models such as the Roofline Model, profile existing algorithms, and propose new parallel computing paths that exploit the selected hardware architecture to accelerate the assigned algorithm.
The topic is suitable for Master's or motivated Bachelor's students.
- Bachelor/Master
- Supervisor: Dr.-Ing. Daniele Passaretti