Lehrstuhl Hardware-nahe Technische Informatik

Publikationen

2020

Begutachteter Zeitschriftenartikel

Joseph, Jan Moritz;  Ermel, Dominik;  Bamberg, Lennart;  García-Oritz, Alberto;  Pionteck, Thilo 

Application-specific SoC design using core mapping to 3D mesh NoCs with nonlinear area optimization and simulated annealing
In: Technologies: open access journal - Basel: MDPI, 2013, Bd. 8.2020, 1, insges. 10 S.

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Buchbeitrag

Drewes, Anna;  Joseph, Jan Moritz;  Gurumurthy, Balasubramanian;  Broneske, David;  Saake, Gunter;  Pionteck, Thilo 

Optimising operator sets for analytical database processing on FPGAs
In: Applied Reconfigurable Computing. Architectures, Tools, and Applications: 16th International Symposium, ARC 2020, Toledo, Spain, April 13, 2020, Proceedings - Cham: Springer International Publishing, 2020; Rincón, Fernando . - 2020, S. 30-44 - (Lecture Notes in Computer Science; volume12083)

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2019

Begutachteter Zeitschriftenartikel

Bamberg, Lennart;  Joseph, Jan Moritz;  Pionteck, Thilo;  Garcia-Ortiz, Alberto 

Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment
In: Integration, the VLSI journal - Amsterdam [u.a.]: Elsevier Science, Bd. 67.2019, S. 60-72

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Joseph, Jan Moritz;  Bamberg, Lennart;  Ermel, Dominik;  Perjikolaei, Behnam Razi;  Drewes, Anna;  García Ortiz, Alberto;  Pionteck, Thilo 

NoCs in heterogeneous 3D SoCs - co-design of routing strategies and microarchitectures
In: IEEE access: practical research, open solutions/ Institute of Electrical and Electronics Engineers - New York, NY: IEEE, 2013, Bd. 7.2019, S. 135145-135163

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Joseph, Jan Moritz;  Bamberg, Lennart;  Hajjar, Imad;  Schmidt, Robert;  Pionteck, Thilo;  García-Ortiz, Alberto 

Simulation environment for link energy estimation in networks-on-chip with virtual channels
In: Integration, the VLSI journal - Amsterdam [u.a.]: Elsevier Science, 2019

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Buchbeitrag

Joseph, Jan Moritz;  Ermel, Dominik;  Drewes, Anna;  Bamberg, Lennart;  Garcia-Oritz, Alberto;  Pionteck, Thilo 

Area optimization with non-linear models in core mapping for system-on-chips
In: 2019 8th International Conference on Modern Circuits and Systems Technologies (MOCAST) - [Piscataway, NJ]: IEEE

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Drewes, Anna;  Joseph, Jan Moritz;  Gurumurthy, Bala;  Broneske, David;  Saake, Gunter;  Pionteck, Thilo 

Efficient inter-kernel communication for OpenCL database operators on FPGAs
In: 2018 International Conference on Field-Programmable Technology (FPT) - [Piscataway, NJ]: IEEE, 2019

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Blochwitz, Christopher;  Wolff, Julian;  Berekovic, Mladen;  Heinrich, Dennis;  Groppe, Sven;  Joseph, Jan Moritz;  Pionteck, Thilo 

Hardware-accelerated index construction for semantic web
In: 2018 International Conference on Field-Programmable Technology (FPT) - [Piscataway, NJ]: IEEE, 2019

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Dissertation

Joseph, Jan Moritz;  Pionteck, Thilo [AkademischeR BetreuerIn] 

Networks-on-Chip for heterogeneous 3D Systems-on-Chip
In: Magdeburg, 2019, xiv, 248 Seiten, Illustrationen, Diagramme, 30 cm ; [Literaturverzeichnis: Seite 235-246]

2018

Buchbeitrag

Drewes, Tobias;  Joseph, Jan Moritz;  Pionteck, Thilo 

An FPGA-based prototyping framework for Networks-on-Chip
In: 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig17): Cancun, Mexico, December 4-6, 2017 - Piscataway, NJ: IEEE, insges. 7 S., 2018

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Bamberg, Lennart;  Joseph, Jan Moritz;  Schmidt, Robert;  Pionteck, Thilo;  Garcia-Ortiz, Alberto 

Coding-aware link energy estimation for 2D and 3D networks-on-chip with virtual channels
In: 2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018): 2-4 July 2018, Spain - Piscataway, NJ: IEEE, S. 222-228

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Blochwitz, Christopher;  Klink, Raphael;  Joseph, Jan Moritz;  Pionteck, Thilo 

Continuous live-tracing as debugging approach on FPGAs
In: 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig17): Cancun, Mexico, December 4-6, 2017 - Piscataway, NJ: IEEE, insges. 8 S., 2018

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Joseph, Jan Moritz;  Mey, Morten;  Ehlers, Kristian;  Blochwitz, Christopher;  Winker, Tobias;  Pionteck, Thilo 

Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS
In: 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig17): Cancun, Mexico, December 4-6, 2017 - Piscataway, NJ: IEEE, insges. 8 S., 2018

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Joseph, Jan Moritz;  Bamberg, Lennart;  Krell, Gerald;  Hajjar, Imad;  Garcia-Oritz, Alberto;  Pionteck, Thilo 

Specification of simulation models for NoCs in heterogeneous 3D SoCs
In: Proceedings of the 13th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC): July 9th-11th, 2018, Lille, France - Piscataway, NJ: IEEE, insges. 8 S.

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2017

Begutachteter Zeitschriftenartikel

Joseph, Jan Moritz;  Blochwitz, Christopher;  García Ortiz, Alberto;  Pionteck, Thilo 

Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs$Jan Moritz Joseph, ChristopherBlochwitz, Alberto García-Ortiz, Thilo Piontecka
In: Microprocessors and microsystems - Amsterdam [u.a.]: Elsevier, 1979, Bd. 48.2017, S. 36-47

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Buchbeitrag

Drewes, Tobias;  Joseph, Jan Moritz;  Pionteck, Thilo 

An FPGA-based prototyping framework for networks-on-Chip
In: ReConFig\'17: 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ: IEEE ; [Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig\'17, Cancun, Mexico, December 4-6, 2017; poster session A]

Blochwitz, Christopher;  Klink, Raphael;  Joseph, Jan Moritz;  Pionteck, Thilo 

Contentious live-tracing as debugging approach on FPGAS
In: ReConFig\'17: 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ: IEEE ; [Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig\'17, Cancun, Mexico, December 4-6, 2017; General session]

Joseph, Jan Moritz;  Bamberg, Lennart;  Wrieden, Sven;  Ermel, Dominik;  García-Oritz, Alberto;  Pionteck, Thilo 

Design method for asymmetric 3D interconnect architectures with high level models
In: 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017): July 12-14, 2017, Madrid, Spain : proceedings - [Piscataway, NJ]: IEEE, insges. 8 S.

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Joseph, Jan Moritz;  Mey, Morten;  Ehlers, Kristian;  Blochwitz, Christopher;  Winker, Tobias;  Pionteck, Thilo 

Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS
In: ReConFig\'17: 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ: IEEE ; [Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig\'17, Cancun, Mexico, December 4-6, 2017; Poster session B]

Blochwitz, Christopher;  Wolff, Julian;  Joseph, Jan Moritz;  Werner, Stefan;  Heinrich, Dennis;  Groppe, Sven;  Pionteck, Thilo 

Hardware-accelerated radix-tree based string sorting for big data applications
In: Architecture of Computing Systems - ARCS 2017 - 30th International Conference, Vienna, Austria, April 36, 2017, Proceedings - Cham: Springer, 2017 . - 2017, S. 47-58 - (Lecture Notes in Computer Science; 10172)

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2016

Buchbeitrag

Joseph, Jan Moritz;  Wrieden, Sven;  Blochwitz, Christopher;  García Ortiz, Alberto;  Pionteck, Thilo 

A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip
In: 2016 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoc): June 27-29, 2016, Tallinn, Estonia - [Piscataway, NJ]: IEEE

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Joseph, Jan Moritz;  Blochwitz, Christioher;  Pionteck, Thilo 

Adaptive allocation of default router paths in Network-on-Chips for latency reduction
In: Proceedings of the 2016 International Conference on High Performance Computing & Simulation (HPCS 2016): July 18-22, 2016, Innsbruck, Austria - Piscataway, NJ: IEEE

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Joseph, Jan Moritz;  Winker, Tobias;  Ehlers, Christian;  Blochwitz, Christopher;  Pionteck, Thilo 

Hardware-accelerated pose estimation for embedded systems using vivado HLS
In: ReConFig: 2016 International Conference on Reconfigurable Computing and FPGAs : November 30 - December 2, Cancun, Mexico - Piscataway, NJ: IEEE ; [Kongress: 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig, Cancun, Mexico, November 30 - December 2, 2016]

2015

Herausgeberschaft

Joseph, Jan Moritz;  Blochwitz, Christopher;  Pionteck, Thilo;  Garcia-Ortiz, Alberto 

Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs
In: 2015, S. 1-4, 10.1109/NORCHIP.2015.7364370

2014

Herausgeberschaft

Joseph, Jan Moritz;  Pionteck, Thilo 

A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling
In: 2014, S. 1-6, 10.1109/ISSOC.2014.6972440

Letzte Änderung: 01.07.2020 - Ansprechpartner: Webmaster