Lehrstuhl Hardware-nahe Technische Informatik

Dr.-Ing. Jan Moritz Joseph

Wiss. Mitarbeiter/-in

Dr.-Ing. Jan Moritz Joseph

Institut für Informations- und Kommunikationstechnik (IIKT)
Lehrstuhl Hardware-nahe Technische Informatik
,
Vita

Dr.-Ing. Jan Moritz Joseph ist seit Juli 2020 an der RWTH Aachen beschäftigt.

Institut für Kommunikationstechnologie und Eingebettete Systeme

Linkedin

Lebenslauf

Dr.-Ing. Jan Moritz Joseph wurde in Berlin im Jahr 1990 geboren. Er hat seinen B.Sc. Abschluss im Fach Medizinische Ingenieurwissenschaften im Jahr 2011 und seinen M.Sc. Abschluss in Informatik in 2014 von der Universität zu Lübeck erhalten. Von 2008 bis 2014 war er Stipendiat der Studienstiftung des Deutschen Volkes. Im August 2019 erhiet er seine Promotion mit dem Prädikat "summa cum laude" über das Thema "Networks-on-Chip for heterogeneous 3D Systems-on-Chip" verliehen durch die Fakultät für Elektro- und Informationstechnik durch die Otto-von-Guericke Universität Magdeburg. Von September 2019 bis März 2020 ist Herr Dr. Joseph als Visiting Research Scholar amGeorgia Institute of Technologie tätig in Prof. Tushar Krishnas Gruppe. Außerdem arbeitet er im Moment als PostDoc an der Otto-von-Guericke-Universität Magdeburg am Institut für Informations- und Kommunikationstechnik.

Der Fokus von Herrn Joseph Tätigkeit liegt auf der Erforschung von Kommunikationsarchitekturen für heterogene 3D Integration in verschiedenen Anwendungsgebieten. Aktuell liegt der Fokus auf systlischen Arrays als Beschleunigerarchitekturen für CNNs. Auch nach seiner Promotion untersucht er weiterhin Network-on-Chips, da diese eine skalierbare Kommunikationsinfrastuktur für moderne Mehrkernsysteme darstellen. Seine zwei Bereiche besonderen Interesses sind die Priorisierung von semi-statischen Datenströmen für on-chip Netzwerke und asymmetrische 3D-Network-on-Chips.

Forschungsschwerpunkte

  • Kommunikationsnetze
  • heterogene 3D Integration
  • Computer Architecture
  • EDA Optimiung und Entwurf von Network-on-Chips (NoCs) und System-on-Chips (SoCs)
  • Modellierung und Simulation

Projekte

  • Bearbeitung von DFG-Project "Erkennung und adaptive Priorisierung von semi-statischen Datenströmen und von Verkehrsstrommustern in Network-on-Chips"
  • Bearbeitung von DFG-Project "Technology-aware Asymmetric 3D-Interconnect Architectures: Templates and Design Methods"
  • Ratatoskr: Framework for in-depth PPA analysis for 3D-NoCs, zu finden auf Github

Abschlussarbeiten

Ich biete gerne Abschlussarbeiten zu aktuellen Forschungsthemen an. Eine Übersicht über aktuelle Themen finden Sie hier. Themen können nach Rücksprache ggf. in Projekten bearbeitet werden.

HiWis gesucht!

Wir sind auf der Suche nach HiWis, die an unserem Forschungsprojekt über A-3D-NoCs mitarbeiten möchten. Hier finden Sie eine Beschreibung der Aufgaben, aktuelle Themen, und Anforderungen.

Veröffentlichungen

vollwertige Veröffentlichungen
2020 Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg, Alberto García-Ortiz, Thilo Pionteck: “Application-Specific SoC Design Using Core Mapping to 3D Mesh NoCs with Nonlinear Area Optimization and Simulated Annealing”, Technologies 8.1 (2020): 10.
2020 Ananda Samajdar, Jan Moritz Joseph, Yuhao Zhu, Paul Whatmough, Matthew Mattina, Tushar Krishna: “A Systematic Methodology for Characterizing Scalability of DNN Accelerators”, International Symposium on Performance Analysis of Systems and Software (ISPASS), Boston, MA (accepted, unpublished).
2020 Anna Drewes, Jan Moritz Joseph, Bala Gurumurthy, David Broneske, Sajjad Tamimi, Gunter Saake, Thilo Pionteck: “Optimising Operator Sets for Analytical Database Processing on FPGAs”, International Symposium on Applied Reconfigurable Computing (ARC), Toledo, Spain (accepted, unpublished).
2019 Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg, Alberto García-Ortiz, Thilo Pionteck: “System-level optimization of Network-on-Chips for heterogeneous 3D System-on-Chips”, International Conference on Computer Design (ICCD), Abu Dhabi, VAE, doi: 10.1109/ICCD46524.2019.000. Acceptance rate: 31.8%
2019 Joseph, J. M., Bamberg, L., Ermel, D., Perjikolaei, B. R., Drewes, A., García-Oritz, A., & Pionteck, T. (2019). NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures. IEEE Access, 10.1109/ACCESS.2019.2942129, 2019.
2019 JM Joseph, L Bamberg, I Hajjar, R Schmidt, T Pionteck, A García-Ortiz: Simulation environment for link energy estimation in networks-on-chip with virtual channels, Integration.
2019 L Bamberg, JM Joseph, T Pionteck, A Garcia-Ortiz: Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment, Integration 67, 60-72
2019 Jan Moritz Joseph, Dominik Ermel, Tobias Drewes, Lennart Bamberg, Alberto Garcia-Ortiz, and Thilo Pionteck: Area Optimization with Non-linear Models in Core Mapping for System-on-Chips, MOCAST, Thessaloniki, Greece, 2019. 10.1109/MOCAST.2019.8742035
2018 Jan Moritz Joseph, Lennart Bamberg, Krell Gerald, Hajjar Imad, Alberto Garcia-Ortiz, and Thilo Pionteck: Specification of Simulation Models for NoCs in Heterogeneous 3D SoCs, ReCoSoC, France, 2018.
2018 Lennart Bamberg, Jan Moritz Joseph, Robert Schmidt, Thilo Pionteck and Alberto Garcia-Ortiz: Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels, PATMOS, Spain, 2018.
2018 T. Drewes, J. M. Joseph, B. Gurumurthy, D. Broneske, G. Saake and T. Pionteck, "Efficient Inter-Kernel Communication for OpenCL Database Operators on FPGAs," 2018 International Conference on Field-Programmable Technology (FPT), Naha, Okinawa, Japan, 2018, pp. 266-269. 10.1109/FPT.2018.00050
2018 C. Blochwitz, J Wolff, M Berekovic, D Heinrich, S Groppe, JM Joseph, T Pionteck, "Hardware-Accelerated Index Construction for Semantic Web," 2018 International Conference on Field-Programmable Technology (FPT), Naha, Okinawa, Japan, 2018, pp. 278-281. 10.1109/FPT.2018.00053
2017 Jan Moritz Joseph, Morten Mey, Kristian Ehlers, Christopher Blochwitz, Tobias Winker, Thilo Pionteck: Design Space Exploration for a Hardware-accelerated Embedded Real-Time Pose Estimation using Vivado HLS, Reconfig, Cancun, Mexico, 2017.
2017 Tobias Drewes, Jan Moritz Joseph, Thilo Pionteck: An FPGA-based Prototyping Framework for Networks-on-Chip, Reconfig, Cancun, Mexico, 2017.
2017 Christopher Blochwitz, Raphael Klink, Jan Moritz Joseph, Thilo Pionteck: Continuous Live-Tracing as Debugging Approach on FPGAs, Reconfig, Cancun, Mexico, 2017.
2017 Jan Moritz Joseph, Lennart Bamberg, Sven Wrieden, Dominik Ermel, Alberto Garcia-Oritz, Thilo Pionteck: Design Method for Asymmetric 3D-Interconnect Architectures with High Level Models, ReCoSoC, Madrid, Spain, 2017.
2017 Jan Moritz Joseph, Christopher Blochwitz, Alberto García-Ortiz, Thilo Pionteck: Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs, MICPRO 2460, 2017.
2016 Christopher Blochwitz, Julian Wolff, Jan Moritz Joseph, Stefan Werner, Dennis Heinrich, Sven Groppe, Thilo Pionteck: Hardware-accelerated Radix-Tree based string sorting for Big Data applications, ARCS 2017.
2016 Jan Moritz Joseph, Tobias Winker, Kritian Ehlers, Christopher Blochwitz, Thilo Pionteck: Hardware-Accelerated Pose Estimation for Embedded Systems using Vivado HLS , Reconfig, Cancun, Mexiko, 2016. preprint, poster
2016 Jan Moritz Joseph, Sven Wrieden, Christopher Blochwitz, Alberto García-Ortiz, Thilo Pionteck: A Simulation Environment for Design Space Exploration for Asymmetric 3D-Network-on-Chip, 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016), Tallinn, 2016. presentation, preprint
2016 Jan Moritz Joseph, Christopher Blochwitz, Thilo Pionteck: Adaptive Allocation of Default Router Paths in Network-on-Chips for Latency Reduction, 2016 International Conference on High Performance Computing & Simulation (HPCS), Innsbruck, 2016. presentation, preprint
2015 Jan Moritz Joseph, Christopher Blochwitz, Alberto García-Ortiz, Thilo Pionteck: Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs, Nordic Circuits and Systems Conference (NORCAS), Oslo, 2015. preprint
2015 Christopher Blochwitz, Jan Moritz Joseph, Rico Backasch, Stefan Werner, Dennis Heinrich, Sven Groppe, Thilo Pionteck; An optimized Radix-Tree for hardware-accelerated index generation for Semantic Web Databases, Reconfig, Cancun, Mexiko, 2015
2015 Jan Moritz Joseph, Thilo Pionteck; A Cycle-Accurate Network-on-Chip Simulator with Support for Abstract Task Graph, International Symposium on System-on-Chip, Tampere, 2014. presentation, preprint
Poster und kleinere Konferenzbeiträge
  • Jan Moritz Joseph, Philipp Forster, Matthias Hudecek; "Digitalisierung von Change Management", 3. Tagung für Führung und Organisation, Berlin, 2016
  • Jan Moritz Joseph, Jens Christian Claussen; "Dynamical model of the scientific process: Knowledge generation embedded in the scientific map of science", DPG Spring Meeting, Regensburg, 2016
  • Jan Moritz Joseph, Matthias Hudecek; "Measurability and Characteristics of Structural Metrics and Business Scores for HR development", DPG Spring Meeting, Regensburg, 2016
  • Jan Moritz Joseph, Jens Christian Claussen; "Modeling the evolution of science in scientific space", DPG Spring Meeting, Berlin, 2015
  • Jan Moritz Joseph, Jens Christian Claussen; "A dynamical author-strategic growth model for the structure of science in scientific space", XXXIV Dynamics Days Europe, Bayreuth, 2014
  • Jan Moritz Joseph, Jens Christian Claussen; "A Dynamical Model of Scientific Collaboration Networks", DPG Spring Meeting, Dresden, 2014

Disclaimer: Preprints are offered in compliance with the IEEE copyright policy: An FAQ on Intellectual Property Rights for IEEE Authors

Gutachtertätigkeit

Microprocessors and Microsystems, Elsevier; IEEE Transactions on Industrial Electronics

Betreute Abschlussarbeiten

  • Tobias Winker. Generierung einer Hardwarebeschleunigung zur Gestenerkennung auf einem Xilinx Zynq unter Verwendung von High Level Synthesis. Bachelorarbeit, Universität zu Lübeck, 2016.
  • Morten Mey. Entwurf und Implementierung eines hardwarebeschleunigten Algorithmus zur Gestenerkennung. Masterarbeit, Universität zu Lübeck, 2016.
  • Tobias Drewes, Implementierung und Evaluation einer Adaptiven Auswahl von Standardpfaden in NoCs. Masterarbeit, Universität zu Lübeck, 2016.
Publikationen

2020

Begutachteter Zeitschriftenartikel

Joseph, Jan Moritz;  Ermel, Dominik;  Bamberg, Lennart;  García-Oritz, Alberto;  Pionteck, Thilo 

Application-specific SoC design using core mapping to 3D mesh NoCs with nonlinear area optimization and simulated annealing
In: Technologies: open access journal - Basel: MDPI, 2013, Bd. 8.2020, 1, insges. 10 S.

Buchbeitrag

Drewes, Anna;  Joseph, Jan Moritz;  Gurumurthy, Balasubramanian;  Broneske, David;  Saake, Gunter;  Pionteck, Thilo 

Optimising operator sets for analytical database processing on FPGAs
In: Applied Reconfigurable Computing. Architectures, Tools, and Applications: 16th International Symposium, ARC 2020, Toledo, Spain, April 13, 2020, Proceedings - Cham: Springer International Publishing, 2020; Rincón, Fernando . - 2020, S. 30-44 - (Lecture Notes in Computer Science; volume12083)

2019

Begutachteter Zeitschriftenartikel

Bamberg, Lennart;  Joseph, Jan Moritz;  Pionteck, Thilo;  Garcia-Ortiz, Alberto 

Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment
In: Integration, the VLSI journal - Amsterdam [u.a.]: Elsevier Science, Bd. 67.2019, S. 60-72

Joseph, Jan Moritz;  Bamberg, Lennart;  Ermel, Dominik;  Perjikolaei, Behnam Razi;  Drewes, Anna;  Garcia-Ortiz, Alberto;  Pionteck, Thilo 

NoCs in heterogeneous 3D SoCs - co-design of routing strategies and microarchitectures
In: IEEE access - New York, NY: IEEE, Bd. 7.2019, S. 135145-135163

Joseph, Jan Moritz;  Bamberg, Lennart;  Hajjar, Imad;  Schmidt, Robert;  Pionteck, Thilo;  García-Ortiz, Alberto 

Simulation environment for link energy estimation in networks-on-chip with virtual channels
In: Integration, the VLSI journal - Amsterdam [u.a.]: Elsevier Science, 2019

Buchbeitrag

Joseph, Jan Moritz;  Ermel, Dominik;  Drewes, Anna;  Bamberg, Lennart;  Garcia-Oritz, Alberto;  Pionteck, Thilo 

Area optimization with non-linear models in core mapping for system-on-chips
In: 2019 8th International Conference on Modern Circuits and Systems Technologies (MOCAST) - [Piscataway, NJ]: IEEE

Drewes, Anna;  Joseph, Jan Moritz;  Gurumurthy, Bala;  Broneske, David;  Saake, Gunter;  Pionteck, Thilo 

Efficient inter-kernel communication for OpenCL database operators on FPGAs
In: 2018 International Conference on Field-Programmable Technology (FPT) - [Piscataway, NJ]: IEEE, 2019

Blochwitz, Christopher;  Wolff, Julian;  Berekovic, Mladen;  Heinrich, Dennis;  Groppe, Sven;  Joseph, Jan Moritz;  Pionteck, Thilo 

Hardware-accelerated index construction for semantic web
In: 2018 International Conference on Field-Programmable Technology (FPT) - [Piscataway, NJ]: IEEE, 2019

Dissertation

Joseph, Jan Moritz;  Pionteck, Thilo [AkademischeR BetreuerIn] 

Networks-on-Chip for heterogeneous 3D Systems-on-Chip
In: Magdeburg, 2019, xiv, 248 Seiten, Illustrationen, Diagramme, 30 cm ; [Literaturverzeichnis: Seite 235-246]

2018

Buchbeitrag

Drewes, Tobias;  Joseph, Jan Moritz;  Pionteck, Thilo 

An FPGA-based prototyping framework for Networks-on-Chip
In: 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig17): Cancun, Mexico, December 4-6, 2017 - Piscataway, NJ: IEEE, insges. 7 S., 2018

Bamberg, Lennart;  Joseph, Jan Moritz;  Schmidt, Robert;  Pionteck, Thilo;  Garcia-Ortiz, Alberto 

Coding-aware link energy estimation for 2D and 3D networks-on-chip with virtual channels
In: 2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018): 2-4 July 2018, Spain - Piscataway, NJ: IEEE, S. 222-228

Blochwitz, Christopher;  Klink, Raphael;  Joseph, Jan Moritz;  Pionteck, Thilo 

Continuous live-tracing as debugging approach on FPGAs
In: 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig17): Cancun, Mexico, December 4-6, 2017 - Piscataway, NJ: IEEE, insges. 8 S., 2018

Joseph, Jan Moritz;  Mey, Morten;  Ehlers, Kristian;  Blochwitz, Christopher;  Winker, Tobias;  Pionteck, Thilo 

Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS
In: 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig17): Cancun, Mexico, December 4-6, 2017 - Piscataway, NJ: IEEE, insges. 8 S., 2018

Joseph, Jan Moritz;  Bamberg, Lennart;  Krell, Gerald;  Hajjar, Imad;  Garcia-Oritz, Alberto;  Pionteck, Thilo 

Specification of simulation models for NoCs in heterogeneous 3D SoCs
In: Proceedings of the 13th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC): July 9th-11th, 2018, Lille, France - Piscataway, NJ: IEEE, insges. 8 S.

2017

Begutachteter Zeitschriftenartikel

Joseph, Jan Moritz;  Blochwitz, Christopher;  García Ortiz, Alberto;  Pionteck, Thilo 

Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs$Jan Moritz Joseph, ChristopherBlochwitz, Alberto García-Ortiz, Thilo Piontecka
In: Microprocessors and microsystems - Amsterdam [u.a.]: Elsevier, 1979, Bd. 48.2017, S. 36-47

Buchbeitrag

Drewes, Tobias;  Joseph, Jan Moritz;  Pionteck, Thilo 

An FPGA-based prototyping framework for networks-on-Chip
In: ReConFig\'17: 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ: IEEE ; [Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig\'17, Cancun, Mexico, December 4-6, 2017; poster session A]

Blochwitz, Christopher;  Klink, Raphael;  Joseph, Jan Moritz;  Pionteck, Thilo 

Contentious live-tracing as debugging approach on FPGAS
In: ReConFig\'17: 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ: IEEE ; [Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig\'17, Cancun, Mexico, December 4-6, 2017; General session]

Joseph, Jan Moritz;  Bamberg, Lennart;  Wrieden, Sven;  Ermel, Dominik;  García-Oritz, Alberto;  Pionteck, Thilo 

Design method for asymmetric 3D interconnect architectures with high level models
In: 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017): July 12-14, 2017, Madrid, Spain : proceedings - [Piscataway, NJ]: IEEE, insges. 8 S.

Joseph, Jan Moritz;  Mey, Morten;  Ehlers, Kristian;  Blochwitz, Christopher;  Winker, Tobias;  Pionteck, Thilo 

Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS
In: ReConFig\'17: 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ: IEEE ; [Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig\'17, Cancun, Mexico, December 4-6, 2017; Poster session B]

Blochwitz, Christopher;  Wolff, Julian;  Joseph, Jan Moritz;  Werner, Stefan;  Heinrich, Dennis;  Groppe, Sven;  Pionteck, Thilo 

Hardware-accelerated radix-tree based string sorting for big data applications
In: Architecture of Computing Systems - ARCS 2017 - 30th International Conference, Vienna, Austria, April 36, 2017, Proceedings - Cham: Springer, 2017 . - 2017, S. 47-58 - (Lecture Notes in Computer Science; 10172)

2016

Buchbeitrag

Joseph, Jan Moritz;  Wrieden, Sven;  Blochwitz, Christopher;  García Ortiz, Alberto;  Pionteck, Thilo 

A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip
In: 2016 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoc): June 27-29, 2016, Tallinn, Estonia - [Piscataway, NJ]: IEEE

Joseph, Jan Moritz;  Blochwitz, Christioher;  Pionteck, Thilo 

Adaptive allocation of default router paths in Network-on-Chips for latency reduction
In: Proceedings of the 2016 International Conference on High Performance Computing & Simulation (HPCS 2016): July 18-22, 2016, Innsbruck, Austria - Piscataway, NJ: IEEE

Joseph, Jan Moritz;  Winker, Tobias;  Ehlers, Christian;  Blochwitz, Christopher;  Pionteck, Thilo 

Hardware-accelerated pose estimation for embedded systems using vivado HLS
In: ReConFig: 2016 International Conference on Reconfigurable Computing and FPGAs : November 30 - December 2, Cancun, Mexico - Piscataway, NJ: IEEE ; [Kongress: 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig, Cancun, Mexico, November 30 - December 2, 2016]

2015

Herausgeberschaft

Joseph, Jan Moritz;  Blochwitz, Christopher;  Pionteck, Thilo;  Garcia-Ortiz, Alberto 

Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs
In: 2015, S. 1-4, 10.1109/NORCHIP.2015.7364370

2014

Herausgeberschaft

Joseph, Jan Moritz;  Pionteck, Thilo 

A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling
In: 2014, S. 1-6, 10.1109/ISSOC.2014.6972440

Letzte Änderung: 16.06.2020 - Ansprechpartner: Webmaster